NXP Semiconductors
LPC1111/12/13/14
RESET/PIO0_0
PIO0_1/CLKOUT/CT32B0_MAT2
V SSIO
7
8
9
39 TRST/PIO1_2/AD3/CT32B1_MAT1
38 TDO/PIO1_1/AD2/CT32B1_MAT0
37 TMS/PIO1_0/AD1/CT32B1_CAP0
XTALIN 10
XTALOUT 11
36 TDI/PIO0_11/AD0/CT32B0_MAT3
35 PIO2_11/SCK0
V DD(IO) 12
PIO1_8/CT16B1_CAP0 13
PIO0_2/SSEL0/CT16B0_CAP0 14
PIO2_7 15
PIO2_8 16
PIO2_1/DSR/SCK1 17
Fig 3.
Pin configuration PLCC44 package
LPC1111_12_13_14_0
LPC1114FA44/301
34 PIO1_10/AD6/CT16B1_MAT1
33 SWCLK/PIO0_10/SCK0/CT16B0_MAT2
32 PIO0_9/MOSI0/CT16B0_MAT1
31 PIO0_8/MISO0/CT16B0_MAT0
30 PIO2_2/DCD/MISO1
29 PIO2_10
002aaf020
? NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 00.11 — 13 November 2009
6 of 53
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